1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device capable of preventing an electrical short between a contact and its adjacent contact pad, the contact being electrically connected to an upper conductive layer, and a method of manufacturing the same.
2. Description of the Related Art
With the development of technology for manufacturing semiconductor devices, semiconductor devices are more highly integrated. Accordingly, the size of contacts electrically connecting layers and the distances between the contacts have been reduced. Also, the distances between contact pads have been reduced. The contacts can be a bottom electrode contact of a capacitor and/or a bit line contact.
FIG. 1A is a plan view of a conventional bottom electrode contact 22 contacting with a contact pad. FIG. 1B is a sectional view taken along line 1B-1B of FIG. 1A. For convenience, elements not essential to this description are not shown in FIG. 1.
Referring to FIGS. 1A and 1B, a semiconductor substrate 10 has an active region 12 defined by a device isolation layer 11. Contact pads contacting with the active region 12 pass through a first interlayer insulating layer 24 formed on the semiconductor substrate 10. The contact pads include a bottom electrode contact pad 16 and a bit line contact pad 14. The bottom electrode contact pad 16 is connected with a capacitor bottom electrode contact 22 disposed above the bottom electrode contact pad 16, and the bit line contact pad 14 is connected with a bit line contact 20 disposed above the bit line contact pad 14.
The bit line contact 20 passes through a second interlayer insulating layer 26 formed on the first interlayer insulating layer 24 and the contact pads 14 and 16. The bottom electrode contact 22 passes through a third interlayer insulating layer 28 and the second interlayer insulting layer 26. The third interlayer insulating layer 28 is formed on the bit line contact 20 and the second interlayer insulting layer 26. A bit line structure 30 includes a bit line 31, an insulating layer 32, and a spacer 33 within the third interlayer insulating layer 28. An etching stopping layer 18 can be further formed at the bottom of the second interlayer insulating layer 26 except for a portion where the contact pads 14 and 16 are connected with the contacts 20 and 22.
The contact pads 14 and 16 formed inside the first interlayer insulating layer 24 have thickness equal to that of the first interlayer insulating layer 24. However, as the design rule is scaled down, the distance d between the bottom electrode contact 22 and its adjacent bit line contact pad 14 becomes shorter. If the distance d becomes shorter, the contacts 20 and 22 and their adjacent contact pads 14 and 16 may be electrically shorted.